Silicon carbide semiconductor device and method for manufacturing the same

ABSTRACT

A silicon carbide semiconductor device includes: a silicon carbide layer of a first conductive type including a defect region in which a crystal defect exists; a plurality of well regions of a second conductive type formed on the silicon carbide layer; source regions of the first conductive type formed in the well regions; gate oxide films formed on the silicon carbide layer, the well regions and the source regions; gate electrodes formed on the gate oxide films; and a source electrode electrically connected to the well regions and the source regions, wherein the source region is not formed in the defect region.

BACKGROUND OF THE INVENTION Field

The present disclosure relates to a silicon carbide semiconductor deviceand a method for manufacturing the same.

Background

A silicon carbide crystal is promising as a material of anext-generation switching device which can realize high voltageresistance, low loss and high-temperature operation (see, for example,JP 2012-244083 A).

SUMMARY

However, a silicon carbide crystal involves a number of crystal defectssuch as a stacking fault. In a conventional silicon carbidesemiconductor device, there is a problem in that as a result of a leakcurrent occurring due to a crystal defect in a wafer or a crystal defectoccurring upon epitaxial growth, a yield degrades.

The present disclosure has been made to solve the problem as describedabove, and an object of the present disclosure is to obtain a siliconcarbide semiconductor device which can improve a yield, and a method formanufacturing the same.

A silicon carbide semiconductor device according to the presentdisclosure includes: a silicon carbide layer of a first conductive typeincluding a defect region in which a crystal defect exists; a pluralityof well regions of a second conductive type formed on the siliconcarbide layer; source regions of the first conductive type formed in thewell regions; gate oxide films formed on the silicon carbide layer, thewell regions and the source regions; gate electrodes formed on the gateoxide films; and a source electrode electrically connected to the wellregions and the source regions, wherein the source region is not formedin the defect region.

In the present disclosure, the source region is not formed in the defectregion. If the source region is not formed, because a transistor is notturned on even if a voltage is applied to the gate electrode, a leakcurrent does not occur. As a result, it is possible to improve a yield.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view illustrating a silicon carbidesemiconductor device according to a first embodiment.

FIG. 2 is a flowchart of a method for manufacturing the silicon carbidesemiconductor device according to the first embodiment.

FIG. 3 is a plan view illustrating a silicon carbide wafer afterepitaxial growth.

FIG. 4 is a plan view illustrating a state where a region in which anactive region is to be formed in the silicon carbide wafer is specified.

FIG. 5 is an enlarged plan view illustrating crystal defects included ineach chip.

FIG. 6 is an enlarged plan view illustrating crystal defects included ineach chip.

FIG. 7 is a cross-sectional view illustrating the method formanufacturing the silicon carbide semiconductor device according to thefirst embodiment.

FIG. 8 is a cross-sectional view illustrating the method formanufacturing the silicon carbide semiconductor device according to thefirst embodiment.

FIG. 9 is a cross-sectional view illustrating the method formanufacturing the silicon carbide semiconductor device according to thefirst embodiment.

FIG. 10 is a cross-sectional view illustrating the method formanufacturing the silicon carbide semiconductor device according to thefirst embodiment.

FIG. 11 is a cross-sectional view illustrating a silicon carbidesemiconductor device according to a comparative example.

FIG. 12 is a cross-sectional view illustrating a method formanufacturing a semiconductor device according to a second embodiment.

FIG. 13 is a cross-sectional view illustrating a method formanufacturing a semiconductor device according to a second embodiment.

FIG. 14 is a plan view illustrating a method for manufacturing asemiconductor device according to a fourth embodiment.

FIG. 15 is a cross-sectional view illustrating the method formanufacturing the semiconductor device according to the fourthembodiment.

FIG. 16 is a cross-sectional view illustrating a method formanufacturing a semiconductor device according to a fifth embodiment.

FIG. 17 is a cross-sectional view illustrating a method formanufacturing a semiconductor device according to a fifth embodiment.

DESCRIPTION OF EMBODIMENTS

A silicon carbide semiconductor device and a method for manufacturingthe same according to the embodiments of the present disclosure will bedescribed with reference to the drawings. The same components will bedenoted by the same symbols, and the repeated description thereof may beomitted.

First Embodiment

FIG. 1 is a cross-sectional view illustrating a silicon carbidesemiconductor device according to a first embodiment. In the followingdescription, unless otherwise described, a semiconductor device means aMOSFET (Metal Oxide Semiconductor Field Effect Transistor). An N-typesilicon carbide layer 2 is epitaxially grown on a silicon carbidesubstrate 1. The silicon carbide layer 2 includes a defect region 3 inwhich a crystal defect exists. A plurality of P-type well regions 4 areformed on the silicon carbide layer 2. P-type contact regions 5 andN-type source regions 6 are formed in the well regions 4. Note that theP-type contact regions 5 do not have to be provided.

Gate oxide films 7 are formed on the silicon carbide layer 2, the wellregions 4 and the source regions 6. Gate electrodes 8 are formed on thegate oxide films 7. The gate electrodes 8 are covered with interlayerdielectrics 9 such as thermal oxide films. A source electrode 10 isformed on the silicon carbide layer 2 and the interlayer dielectrics 9and is electrically connected to the P-type contact regions 5 and thesource regions 6. A drain electrode 11 is formed on a lower surface ofthe silicon carbide substrate 1. A plurality of cells of the MOSFET areformed in the silicon carbide layer 2 in this manner. As a feature ofthe present embodiment, the source region 6 is not formed in the defectregion 3.

Subsequently, a method for manufacturing the silicon carbidesemiconductor device according to the present embodiment will bedescribed. FIG. 2 is a flowchart of the method for manufacturing thesilicon carbide semiconductor device according to the first embodiment.

First, a crystal defect of the silicon carbide layer 2 which has beenepitaxially grown on the silicon carbide substrate 1 is inspected (stepS1). FIG. 3 is a plan view illustrating a silicon carbide wafer afterepitaxial growth. The epitaxially grown silicon carbide layer 2 includesa plurality of crystal defects such as, mainly, a triangle defect 12, adownfall defect 13 and a carrot defect 14.

FIG. 4 is a plan view illustrating a state where a region in which anactive region is to be formed in the silicon carbide wafer is specified.The active region is a region which actually operates as a MOSFET chipin the completed semiconductor device. A region 15 in which an activeregion is to be formed in the future in the silicon carbide wafer isspecified, and information regarding a crystal defect in the region 15is acquired. As the information of the crystal defect, a size,coordinates and a shape of the crystal defect can be acquired at thesame time by using, for example, a SiC wafer defect inspection andreview system (SICA) manufactured by Lasertec Corporation. FIG. 5 andFIG. 6 are enlarged plan views illustrating crystal defects included ineach chip. While a crystal defect exceeding 100 μm does not exist inFIG. 5, a crystal defect 16 exceeding 100 μm exists in FIG. 6.

Then, defect information is sorted (step S2). A chip having the crystaldefect 16 exceeding 100 μm is determined as being impossible to beimproved to be a good product even if the present embodiment is applied(step S3), and determined as a defect (step S4). Meanwhile, a chipincluding a crystal defect equal to or less than 100 μm is determined asbeing possible to be improved to be a good product regardless of a shapeand the number of crystal defects (step S5). Concerning the chipdetermined as being possible to be improved to be a good product, aposition of the defect region 3 in which the crystal defect exists isspecified.

FIG. 7 to FIG. 10 are cross-sectional views illustrating the method formanufacturing the silicon carbide semiconductor device according to thefirst embodiment. First, as illustrated in FIG. 7, a plurality of wellregions 4 are formed on the silicon carbide layer 2 throughphotoengraving process and injection of aluminum (Al) (step S6). Anegative resist 17 is applied on an entire upper surface of the siliconcarbide layer 2.

Here, a normal mask for exposing the negative resist 17 for forming thesource region 6 is a mask which covers a region in which the sourceregion 6 is to be formed in each well region 4 and which is open inother regions. As illustrated in FIG. 8, the negative resist 17 isexposed using this normal mask. By this means, the negative resist 17outside the region in which the source region 6 is to be formed isexposed and activated. In the drawings, a portion where the negativeresist 17 is activated is indicated as 17 a, and a portion where thenegative resist 17 is not activated is indicated as 17 b.

Then, as illustrated in FIG. 9, the negative resist 17 in the defectregion 3 whose position is specified in advance is locally exposed withlaser and activated using local laser exposure machine. The local laserexposure machine is a commercially available apparatus which can performlocal exposure of nm order.

Then, as illustrated in FIG. 10, the negative resist 17 which has beenexposed and which has been exposed with laser is developed, and theportion 17 b of the negative resist 17 which is not activated is removedwhile the portion 17 a which is activated is left. By this means, anopening is formed in the region in which the source region 6 is to beformed outside the defect region 3, so that it is possible to leave thenegative resist 17 in the defect region 3. The source regions 6 areformed in the well regions 4 by injecting nitrogen (N) into the wellregions 4 as impurities using the developed negative resist 17 as amask. At this time, the source region 6 is not formed in the defectregion 3 in which the negative resist 17 is left (step S7). Thereafter,the negative resist 17 is removed.

Then, the well regions 4 and the source regions 6 are activated throughheat treatment at a high temperature. Thereafter, the gate oxide films7, the gate electrodes 8, the source electrode 10, the drain electrode11, or the like, are formed (step S8). The silicon carbide semiconductordevice according to the present embodiment is manufactured through theabove-described process.

Subsequently, effects of the present embodiment will be describedthrough comparison with a comparative example. FIG. 11 is across-sectional view illustrating a silicon carbide semiconductor deviceaccording to the comparative example. In the comparative example, thesource regions 6 are also formed in the defect region 3. In the defectregion 3, because crystal orientation is disordered, the gate oxide film7 becomes unformed, and as a result of the gate electrode 8 contactingthe silicon carbide layer 2, current leakage occurs. Further, if thereis a dent in the silicon carbide layer 2, current leakage occurs betweenthe source and the drain.

In contrast, in the present embodiment, the source region 6 is notformed in the defect region 3. If the source region 6 is not formed,because a transistor is not turned on even if a voltage is applied tothe gate electrode 8, a leak current does not occur. As a result, it ispossible to improve a yield.

Note that it is possible to prevent occurrence of a leak current in asimilar manner also in a case where the defect region 3 exists across aplurality of cells as well as existing in one cell. While electrons donot flow in a cell in which the source region 6 is not formed, because achip includes equal to or more than several tens of thousands of cells,even if electrons do not flow in several cells, influence is small.

Further, in a case where the defect region 3 exists in one of tworegions in which the source regions 6 are to be formed included in onewell region 4, both source regions 6 are not formed. However, to preventdegradation of characteristics, it is preferable not to form only thesource region 6 in which the defect region 3 exists.

Second Embodiment

FIG. 12 and FIG. 13 are cross-sectional views illustrating a method formanufacturing a semiconductor device according to a second embodiment.In a similar manner to the first embodiment, a crystal defect isinspected, and the well regions 4 are formed. Then, as illustrated inFIG. 12, a first positive resist 18 is applied on the entire uppersurface of the silicon carbide layer 2. Then, in the defect region 3, asecond positive resist 19 is formed on the first positive resist 18through inkjet application. As an inkjet applicator, a commerciallyavailable apparatus which can perform local photoresist application witha radius of several micrometers is used.

Then, as illustrated in FIG. 13, the first and the second positiveresists 18 and 19 in the region where the source regions 6 are to beformed are exposed and developed. Then, the source regions 6 are formedby injecting N into the well regions 4 using the developed first andsecond positive resists 18 and 19 as a mask.

Here, a thickness of the second positive resist 19 is the same as athickness of the first positive resist 18. Therefore, a resist having athickness which is double a normal thickness is applied to the defectregion 3. Therefore, the first positive resist 18 which is located belowthe second positive resist 19 is not exposed, and the developed firstpositive resist 18 is left in the defect region 3. Accordingly, becausethe source region 6 is not formed in the defect region 3 even if N isinjected, it is possible to obtain effects similar to those of the firstembodiment. Other configurations and effects are similar to those of thefirst embodiment.

Third Embodiment

In a similar manner to the first embodiment, a crystal defect isinspected, and the well regions 4 are formed. Then, a resist is appliedon the entire upper surface of the silicon carbide layer 2. In a similarmanner to FIG. 10, the source regions 6 are formed by injecting N intothe well regions 4 using the exposed and developed resist as a mask.Here, in the present embodiment, the resist is exposed using acommercially available mask-less exposure machine. Normal mask data forforming the source regions 6 and mask data in which a position of thedefect region 3 is aligned are generated and prepared for each waferusing the mask-less exposure machine. Then, the resist is exposed on thebasis of the mask data generated by the mask-less exposure machine sothat the developed resist is left in the defect region 3. Therefore,even if impurities are injected, because the source region 6 is notformed in the defect region 3, it is possible to obtain effects similarto those of the first embodiment. Other configurations and effects aresimilar to those of the first embodiment. Note that the resist to beused for exposure by the mask-less exposure machine may be either apositive resist or a negative resist. Further, exposure may be performedeither in units of chip or in units of wafer.

Fourth Embodiment

FIG. 14 is a plan view illustrating a method for manufacturing asemiconductor device according to a fourth embodiment. FIG. 15 is across-sectional view illustrating the method for manufacturing thesemiconductor device according to the fourth embodiment. In a similarmanner to the first embodiment, a crystal defect is inspected, and thewell regions 4 are formed. Then, an insulating film 20 such as a nitridefilm or an oxide film is formed on the entire upper surface of thesilicon carbide layer 2 through CVD. While a thickness of the insulatingfilm 20 is approximately 2 μm, the thickness may be equal to or greaterthan 2 μm. Then, a resist is applied on the entire surface, and theresist above the defect region 3 is left through exposure anddevelopment. After the insulating film 20 is etched using this resist asa mask, the resist is removed. By this means, as illustrated in FIG. 14,the insulating film 20 is left above the defect region 3.

Then, a resist is applied on the entire upper surface of the siliconcarbide layer 2, and normal mask exposure is performed. By this means,as illustrated in FIG. 15, a resist pattern 21 in which regions wherethe source regions 6 are to be formed are respectively open in aplurality of well regions 4 is formed. Then, the source regions 6 areformed by injecting N into the well regions 4 using the resist pattern21 and the insulating film 20 as a mask. Because impurities are notinjected into a portion where the insulating film 20 is formed, thesource region 6 is not formed in the defect region 3. Therefore, it ispossible to obtain effects similar to those of the first embodiment.Other configurations and effects are similar to those of the firstembodiment. Note that the resist pattern 21 may be either a positiveresist pattern or a negative resist pattern.

Fifth Embodiment

FIG. 16 and FIG. 17 are cross-sectional views illustrating a method formanufacturing a semiconductor device according to a fifth embodiment. Ina similar manner to the first embodiment, a crystal defect is inspected,and the well regions 4 are formed. Then, as illustrated in FIG. 16, thesource regions 6 are respectively formed in a plurality of well regions4 by injecting N using a normal resist pattern 22 in which regions wherethe source regions 6 are to be formed are open. At this time, the sourceregions 6 are formed in all the well regions 4 including the well region4 in which the defect region 3 exists. Thereafter, the resist pattern 22is removed.

Then, as illustrated in FIG. 17, a positive resist 23 is applied on theentire upper surface of the silicon carbide layer 2. The positive resist23 in the defect region 3 is removed through exposure and developmentusing mask-less exposure machine or a laser exposure machine. The sourceregion 6 existing in the defect region 3 is canceled by injecting Alinto the defect region 3 using this positive resist 23 as a mask.Because the source region 6 disappears from the defect region 3, it ispossible to obtain effects similar to those of the first embodiment.Other configurations and effects are similar to those of the firstembodiment.

Obviously many modifications and variations of the present disclosureare possible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

The entire disclosure of Japanese Patent Application No. 2020-049005,filed on Mar. 19, 2020 including specification, claims, drawings andsummary, on which the convention priority of the present application isbased, is incorporated herein by reference in its entirety.

The invention claimed is:
 1. A silicon carbide semiconductor devicecomprising: a silicon carbide layer of a first conductive type includinga defect region in which a crystal defect from epitaxial growth exists,the crystal defect having a length on the order of microns; a pluralityof well regions of a second conductive type formed on the siliconcarbide layer; source regions of the first conductive type formed in thewell regions; gate oxide films formed on the silicon carbide layer, thewell regions and the source regions; gate electrodes formed on the gateoxide films; and a source electrode electrically connected to the wellregions and the source regions, wherein the source region is not formedin the defect region.
 2. The silicon carbide semiconductor deviceaccording to claim 1, wherein the crystal defect is a triangle defect.3. The silicon carbide semiconductor device according to claim 1,wherein the crystal defect is a downfall defect.
 4. The silicon carbidesemiconductor device according to claim 1, wherein the crystal defect isa carrot defect.
 5. The silicon carbide semiconductor device accordingto claim 1, wherein every crystal defect in the silicon carbidesemiconductor device is equal to or less than 100 μm in length.